1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor devices and, more particularly, to improving the fabrication sequence in self-aligned contact processes by enhancing the etch endpoint detection of a desired layer.
2. Description of the Related Art
As is well known, in semiconductor manufacturing, different processes can be implemented to fabricate millions of transistors on a semiconductor chip. An exemplary process is a self-aligned contact (SAC) process, which traditionally is implemented in several stages. First, in the silicon nitride (SiN3) spacer etch process stage, a silicon nitride layer is deposited on a surface of substrate having fabricated transistors. As is well known, each transistor includes source/drain diffusion regions, a conductive polysilicon gate, and a dielectric gate oxide. This silicon nitride layer is subsequently etched utilizing a plasma etch process, thereby creating silicon nitride spacers alongside the polysilicon gates. Second, in the stop layer cap deposit process stage, a stop layer (e.g., silicon nitride) is deposited over the gate oxides as well as the source/drain diffusion regions. Next, the interlevel dielectric layer (ILD) is formed in the ILD oxide deposit process stage through successive depositions of a high density plasma (HDP) oxide layer, a tetraethylorthosilicate (TEOS) deposition layer, and an oxide deposition layer (e.g., silicon dioxide).
Next, in the contact lithography process stage, the surface of the ILD layer is patterned using the photoresist mask defining unprotected contact-like portions. Then, in the ILD oxide etch process stage, exposed portions of the ILD layer are selectively removed during an etching process implementing a first set of chemicals. Thereafter, the etching process is repeated in the following stop layer liner etch process stage, wherein the exposed portions of the stop layer (typically, made out of silicon nitride) are removed implementing a second set of chemicals. As is well known, implementing two different sets of chemicals to etch the exposed portions of the ILD oxide layer and silicon nitride stop layer is important, as the removal of silicon nitride requires chemicals with higher selectivity.
Generally, SAC ILD oxide etch and SAC silicon nitride stop layer liner etch implement a dry etching method called plasma etching. The plasma etching process is typically performed in a plasma chamber in which strong electrical fields cause high energy gases containing positively charged ions and negatively charged electrons to be accelerated toward the exposed surface areas of the ILD layer and silicon nitride stop layer. In actuality, the exposed portions of the ILD layer and silicon nitride stop layer are physically removed as a result of being bombarded with positive ions. However, etching the exposed portions of the ILD and silicon nitride stop layers must stop once it has been determined that the ILD and silicon nitride stop layers have been etched through. As a result, it is imperative to implement an endpoint detection method to stop the etching process once the desired layer has been etched through.
Predominantly, either time mode or optical emission spectroscopy is used to detect the etch endpoint of a desired layer. In the time mode, the thickness of the desired layer as well as the etch rate of the material being removed are used to calculate the approximate length of time required to remove the desired layer. However, because the thickness of wafers and layers formed thereon vary, the time mode has proven to be an unreliable and inefficient method for etch endpoint detection. For instance, due to wafer-to-wafer thickness variation, overetching or underetching of the desired layer may occur. By way of example, the former may cause the removal of portions of the underlying silicon substrate layer or polysilicon gate whereas the latter necessitates further work on the wafer so as to remove the remaining exposed portions.
In the alternative optical emission spectroscopy method, the light emitted by the gases within the etch reactant chamber is used to identify the specific material being etched. As the light emission intensity is directly proportional to the concentration of a specific gas within the etch reactant chamber, the endpoint detector can in theory determine when the etching of a desired material has concluded. However, as the changes in the semiconductor substrate fabrication design rules have enabled the fabrication of smaller and smaller semiconductor substrates, the surface area of contacts and vias (i.e., the exposed oxide portions of the ILD layer) have shrunk (for instance, compare a typical contact oxide area which ranges from 2% to 0.5% to an expected contact oxide area of 0.2% in the near future). Consequently, the concentration of the material being etched in the plasma has decreased, thus creating a rather small change in the plasma at etch endpoint. Ultimately, this small change in the plasma results in small changes in the optical emission signal, thus hindering the optical emission endpoint detection process. Additionally, the optical emission endpoint is designed to be monitored through a transparent window defined within etch reactant chamber. However, as the etching process progresses, monitoring optical emission endpoint signal becomes impossible since visibility reduces as etch polymers build up and cover the transparent window over time. As a result, the optical emission endpoint has also proven to be unreliable in etch endpoint detection, as overetching or underetching of the desired layer may occur.
Accordingly, currently, silicon nitride stop layers are being implemented to compensate for the overetching of the underlying layers. However, besides creating a margin for error, silicon nitride stop layers are not required in the fabrication of the semiconductor devices. Thus, the unreliability of the two predominantly implemented etch endpoint detection processes has added two extra fabrications stages to the SAC contact etch processes, unnecessarily increasing the cost associated with SAC contact process while needlessly reducing throughput.
In view of the foregoing, a need exists for a semiconductor fabrication methodology that eliminates extra fabrication stages implemented in a self-aligned contact process thus reducing fabrication cost while increasing wafer throughput.